Biostar I915P-A7 Manuel du propriétaire télécharger pdf (Page 48)

I915P-A7 BIOS Manual

4 Advanced Chipset Features

This submenu allows you to configure the specific features of the chipset installed on your system.

This chipset manage bus speeds and access to system memory resources, such as DRAM. It also

coordinates communications with the PCI bus. The default settings that came with your system

have been optimized and therefore should not be changed unless you are suspicious that the

settings have been changed incorrectly.

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Figure 4. Advanced Chipset Setup

4.1 DRAM TIMING SELECTABLE

When synchronous DRAM is installed, the number of clock cycles of CAS

latency depends on the DRAM timing.

The Ch o ice s : By S PD (default), Manual.

4.2 CAS LATENCY TIME

When synchronous DRAM is installed, the number of clock cycles of CAS

latency depends on the DRAM timing.

The Ch o ice s : 1.5, 2(default), 2.5, and 3.

4.3 DRAM RAS# TO CAS# DELAY

This field let you insert a timing delay between the CAS and RAS strobe

signals, used when DRAM is written to, read from, or refreshed. Fast gives

faster performance; and slow gives more stable performance. This field

applies only when synchronous DRAM is installed in the system.

The Ch o ice s : 4 (default), 3, and 2.

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Biostar I915P-A7 Manuel du propriétaire Page 48