Biostar I915P-A7 Manuel du propriétaire télécharger pdf (Page 49)

I915P-A7 BIOS Manual

4.4 DRAM RAS# PRECHARGE

If an insufficient number of cycles is allowed for RAS to accumulate its

charge before DRAM refresh, the refresh may be incomplete, and the

DRAM may fail to retain data. Fast gives faster performance; and Slow

gives more stable performance. This field applies only when synchronous

DRAM is insta lled in the system.

The Ch o ice s : 4 (default), 3, and 2.

4.5 PRECHARGE DELAY (TRAS)

This item controls the number of DRAM clocks to activate the precharge

delay.

The Ch o ice s : 8 (default), 7, 6, and 5.

4.6 SYSTEM MEMORY FREQUENCY

This item allows you to select the Memory Frequency.

The Cho ices: Auto (default), DDR266, DDR300, and DDR400.

4.7 SLP_S4# ASSERTION WIDTH

This item sets the minimum assertion width of the SLP-S4# signal to

guarantee the DRAM has been safely power-cycled.

4.8 SYSTEM BIOS CACHEABLE

Selecting Enabled allows you caching of the system BIOS ROM at

F0000h~FFFFFh, resulting a better system performance. However, if any

program writes to this memory area, a system error may result.

The Ch o ice s : En a b le d (default), Disabled.

4.9 VIDEO BIOS CACHEABLE

Select Enabled allows caching of the video BIOS, resulting a better

system performance. However, if any program writes to this memory area,

a system error may result.

The Ch o ice s : Disabled, En abl e d (default).

4.10 MEMORY HOLE AT 15M-16M

You can reserve this area of system memory for ISA adapter ROM. When

this area is reserved it cannot be cached. The user information of

peripherals that need to use this area of system memory usually2

discussed their memory requirements.

The Cho ices: Disabled (default), Enabled.

1 2 ... 44 45 46 47 48 49 50 51 52 53 54 ... 65 66

Pas de commentaire

Biostar I915P-A7 Manuel du propriétaire Page 49